Clock divider and CTS

Turbodebug check Design netlist about clk div timing path: Fig. 1 Design/inst_clk_div Fig. 2, 3 Design/inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN Fig. 4 Design/inst_clk_div/inst_clk_div_dff/hic_dnt_out_reg/Q (constraint below create_generated_clock set it as RootPin, but design inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN as RootPin in CTS Spec file, as Fig. 4 Q pin (out_p) connects to Fig. 2 in0 actually) #Constraint create_clock [get_ports clk4x ] -name dummy_clk4x -period 0.5*0.833 -waveform… read more »

no margin

In ECO period, there might be so-called ‘no-margin’ timing situation which means setup margin is not enough for fixing hold violation/add_buffer in the same reg2reg timing path, because besides OCV derating, check setup violation under slow corners and hold violation under fast corners, ratio of delay between SS and FF might be (2.5~3.5):1.

design flow simple

Simplify a general design flow post-floorplan should be: 1st timing driven placement according to constraints, skew/latency was considered as ‘ideal’ zero, optDesign –preCTS. 2nd CTS, optDesign –postCTS. Clock tree have insertion or propagation delay after CTS. 3rd routing, optDesign –postRoute, optDesign –hold -postRoute. Usually, fix setup violation first, then hold violation in order to obtain… read more »

Clock Tree Synthesis

In clock tree synthesis, do ONE thing only, insert CLK INV (NOT CKBUFF !) which could fix rising and falling transition/duty, to min clock tree latency and skew, balance sink/leaf pins which should be balanced, don’t balance pins which should not be balanced. CTS Macro Model Let tool know the segment of clock path latency which… read more »


Sometimes, it is necessary to add constraint, such as set_disable_timing to let tool ignore timing path which should not be checked, critical path would be fixed by tool correctly. set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_master/delay_0] set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_clk_wr/delay_0] #ezp set_disable_timing -from in1 -to pass [get_cells dll_delay_line/delay_0] #ezp set_disable_timing -from in1… read more »


For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. http://www.techdesignforums.com/practice/guides/on-chip-variation-ocv/ For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915…. read more »

update clock latency

Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »


slew_lower_threshold_pct_rise : 30.00 slew_upper_threshold_pct_rise : 70.00 slew_upper_threshold_pct_fall : 70.00 slew_lower_threshold_pct_fall : 30.00 input_threshold_pct_rise : 50.00 output_threshold_pct_fall : 50.00 input_threshold_pct_fall : 50.00 output_threshold_pct_rise : 50.00 slew_derate_from_library : 0.50 To transition, general library data based on 10% – 90%, some library data based on 30% – 70%, but times 2 in order to modify range from 10%… read more »