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Route Archives - Dr. Pei

Columbia VLSI

January 21, 2026

Digital VLSI Circuits Design Design Digital VLSI Circuits Columbia Integrated Systems Laboratory, Columbia University, 2009 Design an 8-bit microcontroller core, implemented in TSMC CMOS process, Digital VLSI Circuits Designed an 8-bit microcontroller core to perform essential functions within the clock distribution system. Score: 95/100 Project Overview: Completed a professional report under the guidance of Professor Kenneth… read more »

design flow simple

July 10, 2015

Simplify a general design flow post-floorplan should be: 1st timing driven placement according to constraints, skew/latency was considered as ‘ideal’ zero, optDesign –preCTS. 2nd CTS, optDesign –postCTS. Clock tree have insertion or propagation delay after CTS. 3rd routing, optDesign –postRoute, optDesign –hold -postRoute. Usually, fix setup violation first, then hold violation in order to obtain… read more »

Prepare files and check netlist

January 23, 2019

1. Which library files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib 2. Which files are about design? Netlist, constraint, IO file, scan def 3. What should be checked before APR? Check library files,… read more »

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