Publications

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Research Contributions

*Denotes equal contribution and co-first authorship

Journal Articles [1–13] (as of April 2026)

[13] Z. Pei*, S. Lu*, L. Shang, S. Jung, Q. Liang, and C. Pan, “Graphene-based interconnect exploration for FPGA design and optimization towards the end of the roadmap,” ACM Transactions on Design Automation of Electronic Systems, 2026. DOI: 10.1145/3810248

[12] Z. Pei, H.-H. Liu, M. Mayahinia, M. Tahoori, F. Catthoor, Z. Tokei, P. Dubey, and C. Pan, “Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025. DOI: 10.1109/TVLSI.2025.3595818

[11] Z. Pei, H.-H. Liu, M. Mayahinia, M. B. Tahoori, F. Catthoor, Z. Tőkei, D. B. Abdi, J. Myers, and C. Pan, “Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2024. DOI: 10.1109/TCSI.2024.3438164

[10] Z. Pei, M. Mayahinia, H.-H. Liu, M. Tahoori, F. Catthoor, Z. Tokei, and C. Pan, “Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes,” IEEE Transactions on Electron Devices, vol. 70, pp. 230-238, 2022. DOI: 10.1109/TED.2022.3225512

[9] Z. Pei, F. Catthoor, Z. Tokei, and C. Pan, “Beyond-Cu Intermediate-Length Interconnect Exploration for SRAM Application,” IEEE Transactions on Nanotechnology, 2022. DOI: 10.1109/TNANO.2022.3157952

[8] Z. Pei, A. Dutta, L. Shang, S. Jung, and C. Pan, “Interconnect Technology/System Co-Optimization for Low-Power VLSI Applications Using Ballistic Materials,” IEEE Transactions on Electron Devices, vol. 68, pp. 3513-3519, 2021. DOI: 10.1109/TED.2021.3077210

[7] Z. Pei, L. Shang, S. Jung, and C. Pan, “Deep Pipeline Circuit for Low-Power Spintronic Devices,” IEEE Transactions on Electron Devices, vol. 68, pp. 1962-1968, 2021. DOI: 10.1109/TED.2021.3059601

[6] M. Mayahinia, T. Marinelli, Z. Pei, H.-H. Liu, C. Pan, Z. Tőkei, F. Catthoor, M.B. Tahoori, “System Scenario-based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes,” ACM Transactions on Embedded Computing Systems (TECS), 2025. DOI: 10.1145/3762649

[5] H.-H. Liu, C. Gilardi, S. M. Salahuddin, Z. Pei, P. Schuddinck, Y. Xiang, P. Weckx, G. Hellings, M. G. Bardon, and J. Ryckaert, “Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2024. DOI: 10.1109/TCSI.2024.3410518

[4] M. Mayahinia, T. Marinelli, Z. Pei, H.-H. Liu, C. Pan, Z. Tokei, F. Catthoor, and M. B. Tahoori, “Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes,” IEEE Embedded Systems Letters, vol. 16, pp. 321-324, 2024. DOI: 10.1109/LES.2024.3444711

[3] H.-H. Liu, P. Schuddinck, Z. Pei, L. Verschueren, H. Mertens, S. M. Salahuddin, G. Hiblot, Y. Xiang, B. T. Chan, and S. Subramanian, “CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark,” IEEE Transactions on Electron Devices, 2023. DOI: 10.1109/TED.2023.3305322

[2] Y. Yuan, M. Du, S. Zhang, and Z. Pei, “Effects of BiNbO₄ on the microstructure and dielectric properties of BaTiO₃-based ceramics,” Journal of Materials Science: Materials in Electronics, vol. 20, pp. 157-162, 2009. DOI: 10.1007/s10854-008-9674-5

[1] Z. Pei, Y. Yuan, S. Zhang, and B. Li, “Studies on Fabrication and Properties of High Temperature Ceramic Capacitors Sintered at Intermediate Temperature,” Materials Reports: Special Issue on Nanomaterials and New Materials, issue 1, pp. 366–369, 2009. DOI: 10.3321/j.issn:1005-023X.2009.z1.108

Conference Proceedings [14–19] (as of May 2026)

[19] Z. Pei*, S. Z. Riam*, K. Mooney, C. Pan, N. Gong, and J. Wang, “Reliability-Driven Sneak Path Current Modeling and Optimization for Passive Memristor Crossbar Arrays,” in Proceedings of the Great Lakes Symposium on VLSI 2026, 2026. DOI: 10.1145/3787109.3815222. Proceedings PDF | Paper PDF | Podcast.

[18] Z. Pei, M. Mayahinia, H.-H. Liu, M. Tahoori, F. Catthoor, Z. Tokei, and C. Pan, “Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect,” in Proceedings of the Great Lakes Symposium on VLSI 2023, 2023, pp. 159-162. DOI: 10.1145/3583781.3590311

[17] Z. Pei, M. Mayahinia, H.-H. Liu, M. Tahoori, S. M. Salahuddin, F. Catthoor, Z. Tokei, and C. Pan, “Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access,” in Proceedings of 2023 24th International Symposium on Quality Electronic Design (ISQED), 2023, pp. 1-1. DOI: 10.1109/ISQED57927.2023.10129316

[16] S. Lu, Z. Pei, L. Shang, S. Jung, Q. Liang, and C. Pan, “Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node,” in Proceedings of 2025 26th International Symposium on Quality Electronic Design (ISQED), 2025, pp. 1-7. DOI: 10.1109/ISQED65160.2025.11014392

[15] S. Lu, Z. Pei, L. Shang, S. Jung, and C. Pan, “A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices,” in Proceedings of 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), 2023, pp. 1123-1127. DOI: 10.1109/MWSCAS57524.2023.10406005

[14] G. Jalilvand, O. Ahmed, K. Bosworth, C. Fitzgerald, Z. Pei, and T. Jaing, “Application of a metallic cap layer to control Cu TSV extrusion,” in Proceedings of 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, pp. 61-66. DOI: 10.1109/ECTC.2017.290

Acknowledged as a key contributor to the research for the book below:

Circuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes

H.-H. Liu and F. Catthoor, “Circuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes,” Springer, 2024. DOI: 10.1007/978-3-031-76109-6

IEEE Journal	TCAS-I	TED	TVLSI	TNANO
2025/08–2026/08 Ranking*	Computer Hardware Design: 2	Microelectronics: 2	Computer Hardware Design: 10	—
2025/08–2026/08 Impact Factor	5.2→5.6	3.2→3.6	3.1→3.2	2.5
2025/02–05 Ranking*	Computer Hardware Design: 3	Microelectronics: 2	Computer Hardware Design: 10	—
2025/02–05 Impact Factor	5.2	2.9	2.8	2.1

*Google Scholar ranking of journals or conferences in the following 2 categories:

Computer Hardware Design

Microelectronics

h5-index is the h-index for articles published in the last 5 complete years. It is the largest number h such that h articles published in 2019–2023 (2025/02–05 Ranking) → 2020–2024 (2025/08–2026/08 Ranking) have at least h citations each.

h5-median for a publication is the median number of citations for the articles that make up its h5-index.

ACM Primary Article Template, Linux Libertine font. Pandoc.

ACM TODAES

IEEE JxCDC

ACM ICONS

IEEE JETCAS

IEEE Design & Test

IEEE ISCAS

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IOP Neuromorphic Computing and Engineering

Elsevier Applied Materials Today

Elsevier Materials Today Chemistry