Sequential cells timing models

Figure 1  Sequential cell timing arcs Consider timing arcs of a sequential cell shown in Figure 1. For synchronous inputs, such as D pin (or SI, SE), there are following timing arcs: i.  Setup check arc (rising and falling) ii.  Hold check arc (rising and falling) For asynchronous inputs, such as CDN pin, there are… read more »

Prepare files and check netlist

1. Which library files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib 2. Which files are about design? Netlist, constraint, IO file, scan def 3. What should be checked before APR? Check library files,… read more »