Configure STA environment

What’s STA environment? Specifying Clocks. Clock uncertainty and Clock latency Generated clocks Input paths constraint Output paths constraint  Timing path groups External attributes modeling  Check design rules Refine timing analysis Point-to-point specification Set up environment for static timing analysis. Specification of correct constraints is important in analyzing STA results. Design environment should be specified accurately… read more »

Prepare files and check netlist

Which files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib Which files are about design? Netlist, constraint, IO file, scan def