Dr. Pei

Electrical and Computer Engineering | STCO

Netlist Archives - Dr. Pei

Digital VLSI Circuits Design Design Digital VLSI Circuits Columbia Integrated Systems Laboratory, Columbia University, 2009 Design an 8-bit microcontroller core, implemented in TSMC CMOS process, Digital VLSI Circuits Designed an 8-bit microcontroller core to perform essential functions within the clock distribution system. Score: 95/100 Project Overview: Completed a professional report under the guidance of Professor Kenneth… read more »

Protected: Why does inserting or removing buffers help fix timing violations?

March 18, 2026

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Configure STA environment

April 14, 2019

What’s STA environment? Specifying Clocks. Clock uncertainty and Clock latency Generated clocks Input paths constraint Output paths constraint Timing path groups External attributes modeling Check design rules Refine timing analysis Point-to-point specification Set up environment for static timing analysis. Specification of correct constraints is important in analyzing STA results. Design environment should be specified accurately… read more »

Prepare files and check netlist

December 13, 2018

Which files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib Which files are about design? Netlist, constraint, IO file, scan def

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Netlist Archives - Dr. Pei

Columbia VLSI

Protected: Why does inserting or removing buffers help fix timing violations?

Configure STA environment

Prepare files and check netlist