The power a circuit dissipates falls into two broad categories: Static power Dynamic power Static Power Static power is the power dissipated by a gate when it is not switching – that is, when it is inactive or static. Static power is dissipated in several ways. The largest percentage of static power results from source-to-drain… read more »
#Constraint set CLK_PHASE_0_SRC “dummy_clk4x” set EDGES {1 3 5} set CLK_PHY_PORT “clk4x” set PERIOD [expr 0.833 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] set PHY_CLK_PERIOD $PERIOD set PHY_HALF [expr 0.5 * $PHY_CLK_PERIOD] set PHY_QUARTER [expr 0.25 * $PHY_CLK_PERIOD] set CTLR_CLK_PERIOD [expr 2 * $PHY_CLK_PERIOD] set PHY_DDL_CLK_PERIOD [expr 0.2 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] create_clock [get_ports $CLK_PHY_PORT ] -name dummy_clk4x… read more »
Sometimes, it is necessary to add constraint, such as set_disable_timing to let tool ignore timing path which should not be checked, critical path would be fixed by tool correctly. set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_master/delay_0] set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_clk_wr/delay_0] #ezp set_disable_timing -from in1 -to pass [get_cells dll_delay_line/delay_0] #ezp set_disable_timing -from in1… read more »
setOptMode -ignorePathGroupsForHold {in2reg reg2reg in2out} -holdTargetSlack 0 -setupTargetSlack 0 -fixHoldAllowSetupTnsDegrade false setOptMode -holdFixingCells {BUFFER_NAME} setDelayCalMode -engine xxx -SIAware true -signoff true set_analysis_view -setup funcPostC_PVT_setup -hold funcPostC_PVT_setup update_constraint_mode -name funcPostC -sdc_files “constraint_file_path” optDesign -postRoute -outDir ./rpts/fix_skew_setup update_constraint_mode -name funcPostC -sdc_files “constraint_file_path” setOptMode -fixHoldAllowSetupTnsDegrade true optDesign -postRoute -hold -outDir ./rpts/fix_skew_hold constraint file set DQS_TSEL_SEL {tsel_dqs_1_opad tsel_dqs_2_opad tsel_dqs_3_opad}… read more »
Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »
slew_lower_threshold_pct_rise : 30.00 slew_upper_threshold_pct_rise : 70.00 slew_upper_threshold_pct_fall : 70.00 slew_lower_threshold_pct_fall : 30.00 input_threshold_pct_rise : 50.00 output_threshold_pct_fall : 50.00 input_threshold_pct_fall : 50.00 output_threshold_pct_rise : 50.00 slew_derate_from_library : 0.50 To transition, general library data based on 10% – 90%, some library data based on 30% – 70%, but times 2 in order to modify range from 10%… read more »
Which files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib Which files are about design? Netlist, constraint, IO file, scan def
Which files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib Which files are about design? Netlist, constraint, IO file, scan def