Trace clock tree

updateStatus -force designIsPlaced selectInst * dbSet selected.pStatus placed setCTSMode -engine ck cleanupSpecifyClockTree specifyClockTree -file /proj/$project_name/work/user/$design_name/$script_path/${design_name}.seperated.trace.ctstch ckSynthesis -check -forceReconvergent -trace /proj/$project_name/work/user/$design_name/$script_path/${design_name}.seperated.trace  

Check clock gating

Figure 1  A clock gating check A clock gating check occurs when a gating signal can control the path of a clock signal at a logic cell. An example is shown in Figure 1. The pin of logic cell connected to clock is called clock pin and pin where gating signal is connected to is gating pin. Logic… read more »

Crosstalk delay on timing verificaiton

Figure 1  Crosstalk in data and clock paths 1.  Setup analysis Launch clock path sees positive crosstalk delay so that data is launched late. Data path sees positive crosstalk delay so that it takes longer for data to reach destination (D pin in capture FF). Capture clock path sees negative crosstalk delay so that data… read more »

same source create_generated_clock -add

#Constraint set CLK_PHASE_0_SRC “dummy_clk4x” set EDGES {1 3 5} set CLK_PHY_PORT “clk4x” set PERIOD [expr 0.833 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] set PHY_CLK_PERIOD $PERIOD set PHY_HALF [expr 0.5 * $PHY_CLK_PERIOD] set PHY_QUARTER [expr 0.25 * $PHY_CLK_PERIOD] set CTLR_CLK_PERIOD [expr 2 * $PHY_CLK_PERIOD] set PHY_DDL_CLK_PERIOD [expr 0.2 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] create_clock [get_ports $CLK_PHY_PORT ] -name dummy_clk4x… read more »


For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915…. read more »

update clock latency

Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »