Menu

    Blog Stats

    • 143,031 hits

Clock

Columbia VLSI

June 16, 2025

Digital VLSI Circuits Design Design Digital VLSI Circuits Columbia Integrated Systems Laboratory, Columbia University, 2009 Design an 8-bit microcontroller core, implemented in TSMC CMOS process, Digital VLSI Circuits Designed an 8-bit microcontroller core to perform essential functions within the clock distribution system. Score: 95/100 Project Overview: Completed a professional report under the guidance of Professor Kenneth… read more »

Software and Hardware vs Time by Grok

February 24, 2025

  ========1======================== Sure! Your request is to analyze the comprehensive performance of Hideo Kojima’s Metal Gear series on PlayStation platforms over time, calculate a weighted performance index (emphasizing fluidity, with stability, SF precision, and dynamic SF included), and plot it using MATLAB with the Y-axis as the index and the X-axis as time. Below, I’ll… read more »

Technology Node vs Year

February 9, 2025

As semiconductor technology advances, gaming platform hardware accelerates to meet the increasing demands of software, enhancing user interaction and enriching entertainment experiences for the general public. For example, popular video games like “Metal Gear” showcase the improvements in graphics and gameplay made possible by these advancements, allowing players to immerse themselves in more dynamic and… read more »

Trace clock tree

December 13, 2018

updateStatus -force designIsPlaced selectInst * dbSet selected.pStatus placed setCTSMode -engine ck cleanupSpecifyClockTree specifyClockTree -file /proj/$project_name/work/user/$design_name/$script_path/${design_name}.seperated.trace.ctstch ckSynthesis -check -forceReconvergent -trace /proj/$project_name/work/user/$design_name/$script_path/${design_name}.seperated.trace  

Check clock gating

April 14, 2019

Figure 1  A clock gating check A clock gating check occurs when a gating signal can control the path of a clock signal at a logic cell. An example is shown in Figure 1. The pin of logic cell connected to clock is called clock pin and pin where gating signal is connected to is gating pin. Logic… read more »

Crosstalk delay on timing verificaiton

April 14, 2019

Figure 1  Crosstalk in data and clock paths 1.  Setup analysis Launch clock path sees positive crosstalk delay so that data is launched late. Data path sees positive crosstalk delay so that it takes longer for data to reach destination (D pin in capture FF). Capture clock path sees negative crosstalk delay so that data… read more »

same source create_generated_clock -add

April 14, 2019

#Constraint set CLK_PHASE_0_SRC “dummy_clk4x” set EDGES {1 3 5} set CLK_PHY_PORT “clk4x” set PERIOD [expr 0.833 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] set PHY_CLK_PERIOD $PERIOD set PHY_HALF [expr 0.5 * $PHY_CLK_PERIOD] set PHY_QUARTER [expr 0.25 * $PHY_CLK_PERIOD] set CTLR_CLK_PERIOD [expr 2 * $PHY_CLK_PERIOD] set PHY_DDL_CLK_PERIOD [expr 0.2 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] create_clock [get_ports $CLK_PHY_PORT ] -name dummy_clk4x… read more »

OCV

July 6, 2015

For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. http://www.techdesignforums.com/practice/guides/on-chip-variation-ocv/ For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915…. read more »

Older Entries »
Sidebar