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Timing

OCV

July 6, 2015

For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. http://www.techdesignforums.com/practice/guides/on-chip-variation-ocv/ For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915…. read more »

update clock latency

April 14, 2019

Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »

.lib

April 14, 2019

slew_lower_threshold_pct_rise : 30.00 slew_upper_threshold_pct_rise : 70.00 slew_upper_threshold_pct_fall : 70.00 slew_lower_threshold_pct_fall : 30.00 input_threshold_pct_rise : 50.00 output_threshold_pct_fall : 50.00 input_threshold_pct_fall : 50.00 output_threshold_pct_rise : 50.00 slew_derate_from_library : 0.50 To transition, general library data based on 10% – 90%, some library data based on 30% – 70%, but times 2 in order to modify range from 10%… read more »

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