updateStatus -force designIsPlaced selectInst * dbSet selected.pStatus placed setCTSMode -engine ck cleanupSpecifyClockTree specifyClockTree -file /proj/$project_name/work/user/$design_name/$script_path/${design_name}.seperated.trace.ctstch ckSynthesis -check -forceReconvergent -trace /proj/$project_name/work/user/$design_name/$script_path/${design_name}.seperated.trace
Figure 1 A clock gating check A clock gating check occurs when a gating signal can control the path of a clock signal at a logic cell. An example is shown in Figure 1. The pin of logic cell connected to clock is called clock pin and pin where gating signal is connected to is gating pin. Logic… read more »
Basics Capacitance extraction for a typical net in a nanometer design consists of contributions from many neighboring conductors. Some of these are grounded capacitance while many others are from traces which are part of other signal nets. The grounded as well as inter-signal capacitance are illustrated in Figure 1. Figure 1 Example of coupled interconnect… read more »
Figure 1 Sequential cell timing arcs Consider timing arcs of a sequential cell shown in Figure 1. For synchronous inputs, such as D pin (or SI, SE), there are following timing arcs: i. Setup check arc (rising and falling) ii. Hold check arc (rising and falling) For asynchronous inputs, such as CDN pin, there are… read more »
Figure 1 Crosstalk in data and clock paths 1. Setup analysis Launch clock path sees positive crosstalk delay so that data is launched late. Data path sees positive crosstalk delay so that it takes longer for data to reach destination (D pin in capture FF). Capture clock path sees negative crosstalk delay so that data… read more »
Two primary checks are setup and hold checks. Once a clock is defined at clock pin of a flip-flop (FF), setup and hold checks are automatically inferred for the FF. Timing checks are generally performed at multiple conditions including worst-case slow condition and best-case fast condition. Typically, worst-case slow condition is critical for setup check… read more »
In ECO period, there might be so-called ‘no-margin’ timing situation which means setup margin is not enough for fixing hold violation/add_buffer in the same reg2reg timing path, because besides OCV derating, check setup violation under slow corners and hold violation under fast corners, ratio of delay between SS and FF might be (2.5~3.5):1.
For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. http://www.techdesignforums.com/practice/guides/on-chip-variation-ocv/ For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915…. read more »
Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »