Figure 1 A clock gating check A clock gating check occurs when a gating signal can control the path of a clock signal at a logic cell. An example is shown in Figure 1. The pin of logic cell connected to clock is called clock pin and pin where gating signal is connected to is gating pin. Logic… read more »
Basics Capacitance extraction for a typical net in a nanometer design consists of contributions from many neighboring conductors. Some of these are grounded capacitance while many others are from traces which are part of other signal nets. The grounded as well as inter-signal capacitance are illustrated in Figure 1. Figure 1 Example of coupled interconnect… read more »
Figure 1 Sequential cell timing arcs Consider timing arcs of a sequential cell shown in Figure 1. For synchronous inputs, such as D pin (or SI, SE), there are following timing arcs: i. Setup check arc (rising and falling) ii. Hold check arc (rising and falling) For asynchronous inputs, such as CDN pin, there are… read more »
Figure 1 Crosstalk in data and clock paths 1. Setup analysis Launch clock path sees positive crosstalk delay so that data is launched late. Data path sees positive crosstalk delay so that it takes longer for data to reach destination (D pin in capture FF). Capture clock path sees negative crosstalk delay so that data… read more »
Two primary checks are setup and hold checks. Once a clock is defined at clock pin of a flip-flop (FF), setup and hold checks are automatically inferred for the FF. Timing checks are generally performed at multiple conditions including worst-case slow condition and best-case fast condition. Typically, worst-case slow condition is critical for setup check… read more »
What’s STA environment? Specifying Clocks. Clock uncertainty and Clock latency Generated clocks Input paths constraint Output paths constraint Timing path groups External attributes modeling Check design rules Refine timing analysis Point-to-point specification Set up environment for static timing analysis. Specification of correct constraints is important in analyzing STA results. Design environment should be specified accurately… read more »
Sometimes, for cross clock domain timing analysis, incorrect timing report from mistake Path Delay due to big source clock paths latency/skew or target paths latency/skew would lead tool report and fix timing violation wrongly. Designer analysis launch clock paths latency/skew and capture clock paths latency/skew, find out which path(s) is/are too long, for example, it… read more »
Clock to a SoC/chip is like blood to a dog body. If you want the pet smart and strong, hematological system would be healthy. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the chip…. read more »
In ECO period, there might be so-called ‘no-margin’ timing situation which means setup margin is not enough for fixing hold violation/add_buffer in the same reg2reg timing path, because besides OCV derating, check setup violation under slow corners and hold violation under fast corners, ratio of delay between SS and FF might be (2.5~3.5):1.
In clock tree synthesis, do ONE thing only, insert CLK INV (NOT CKBUFF !) which could fix rising and falling transition/duty, to min clock tree latency and skew, balance sink/leaf pins which should be balanced, don’t balance pins which should not be balanced. CTS Macro Model Let tool know the segment of clock path latency which… read more »