Clock to a SoC/chip is like blood to a dog body. If you want the pet smart and strong, hematological system would be healthy. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the chip…. read more »
In ECO period, there might be so-called ‘no-margin’ timing situation which means setup margin is not enough for fixing hold violation/add_buffer in the same reg2reg timing path, because besides OCV derating, check setup violation under slow corners and hold violation under fast corners, ratio of delay between SS and FF might be (2.5~3.5):1.
In clock tree synthesis, do ONE thing only, insert CLK INV (NOT CKBUFF !) which could fix rising and falling transition/duty, to min clock tree latency and skew, balance sink/leaf pins which should be balanced, don’t balance pins which should not be balanced. CTS Macro Model Let tool know the segment of clock path latency which… read more »
setOptMode -ignorePathGroupsForHold {in2reg reg2reg in2out} -holdTargetSlack 0 -setupTargetSlack 0 -fixHoldAllowSetupTnsDegrade false setOptMode -holdFixingCells {BUFFER_NAME} setDelayCalMode -engine xxx -SIAware true -signoff true set_analysis_view -setup funcPostC_PVT_setup -hold funcPostC_PVT_setup update_constraint_mode -name funcPostC -sdc_files “constraint_file_path” optDesign -postRoute -outDir ./rpts/fix_skew_setup update_constraint_mode -name funcPostC -sdc_files “constraint_file_path” setOptMode -fixHoldAllowSetupTnsDegrade true optDesign -postRoute -hold -outDir ./rpts/fix_skew_hold constraint file set DQS_TSEL_SEL {tsel_dqs_1_opad tsel_dqs_2_opad tsel_dqs_3_opad}… read more »
For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. http://www.techdesignforums.com/practice/guides/on-chip-variation-ocv/ For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915…. read more »
Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »