OCV

For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. http://www.techdesignforums.com/practice/guides/on-chip-variation-ocv/
For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915.
The number above is OCV derating, which might be given by foundry. The derating might be different in different corners.

CPPR

For clock common path, it is over pessimism for design to OCV derate twice. So tool should remove common path over-pessmisim delay. When check setup violation, required time should add CPPR value, when check hold violation, required time should minus CPPR value.

This example below, check hold violation, clock common path of capture path is 92ps, launch path is 81ps, so 92-81=11ps is CPPR value.

Path 1: VIOLATED Hold Check with Pin databahn_dll_phy_slice_freq_ratio_intfc/combined_rddata_reg_23_/CP 
Endpoint:   databahn_dll_phy_slice_freq_ratio_intfc/combined_rddata_reg_23_/D (v) checked with  leading edge of 'scan_clk_phy'
Beginpoint: dfi_read_datablk/read_datablk_fifo/io_datain_l_reg_7_/Q           (v) triggered by  leading edge of 'scan_clk_phy'
Path Groups: {reg2reg}
Other End Arrival Time          0.251
+ Hold                         -0.007
+ Phase Shift                   0.000
- CPPR Adjustment               0.011
+ Uncertainty                   0.050
= Required Time                 0.282
  Arrival Time                  0.268
  Slack Time                   -0.014
     Clock Rise Edge                      0.000
     = Beginpoint Arrival Time            0.000
     Timing Path:
      ---------------------------------------------------------------------------------------------------------------------------------------  
       Pin                              Arc               Cell              Delay     Arrival    Incr      Slew      Load    Fanout   User     
                                                                                      Time       Delay                                Derate   
      ---------------------------------------------------------------------------------------------------------------------------------------  
      clk_phy                          clk_phy ^                                     0.000                0.150     0.003   1        
      clk_phy_I_xIOx/I                                   CKBD8BWP12T35P140 0.000     0.000      0.000     0.151     0.003   1        0.915
      clk_phy_I_xIOx/Z                 I ^ -> Z ^        CKBD8BWP12T35P140 0.029     0.029      0.000     0.017     0.013            1.000
      data_slice_data_byte_disable/inst_hic_lp_clkgate_dfi_data_byte_disable_phy/hic_dnt_io_clkgate/CP
                                                         CKLNQD8BWP12T35P140
                                                                           0.001     0.030      0.000     0.020     0.013   2        0.915
      data_slice_data_byte_disable/inst_hic_lp_clkgate_dfi_data_byte_disable_phy/hic_dnt_io_clkgate/Q
                                       CP ^ -> Q ^       CKLNQD8BWP12T35P140
                                                                           0.022     0.052      0.000     0.016     0.025            1.000
      clk_phy_dfi_data_byte_en__L1_I0/I
                                                         DCCKND12BWP12T35P140
                                                                           0.005     0.057      0.000     0.026     0.025   3        0.915
      clk_phy_dfi_data_byte_en__L1_I0/ZN
                                       I ^ -> ZN v       DCCKND12BWP12T35P140
                                                                           0.006     0.063      0.000     0.010     0.014            1.000
      clk_phy_dfi_data_byte_en__L2_I0/I
                                                         DCCKND16BWP12T35P140
                                                                           0.002     0.065      0.000     0.013     0.014   1        0.915
      clk_phy_dfi_data_byte_en__L2_I0/ZN
                                       I v -> ZN ^       DCCKND16BWP12T35P140
                                                                           0.007     0.073      0.000     0.009     0.026            1.000
      clk_phy_dfi_data_byte_en__L3_I1/I
                                                         DCCKND16BWP12T35P140
                                                                           0.002     0.075      0.000     0.012     0.026   2        0.915
      clk_phy_dfi_data_byte_en__L3_I1/ZN
                                       I ^ -> ZN v       DCCKND16BWP12T35P140
                                                                           0.006     0.081      0.000     0.007     0.022            1.000
      clk_phy_dfi_data_byte_en__L4_I2/I
                                                         DCCKND16BWP12T35P140
                                                                           0.002     0.083      0.000     0.011     0.022   2        0.915
     Other End Path:
      ---------------------------------------------------------------------------------------------------------------------------------------  
       Pin                              Arc               Cell              Delay     Arrival    Incr      Slew      Load    Fanout   User     
                                                                                      Time       Delay                                Derate   
      ---------------------------------------------------------------------------------------------------------------------------------------  
      clk_phy                          clk_phy ^                                     0.000                0.150     0.003   1        
      clk_phy_I_xIOx/I                                   CKBD8BWP12T35P140 0.000     0.000      0.000     0.151     0.003   1        1.000
      clk_phy_I_xIOx/Z                 I ^ -> Z ^        CKBD8BWP12T35P140 0.033     0.033      0.000     0.017     0.013            1.139
      data_slice_data_byte_disable/inst_hic_lp_clkgate_dfi_data_byte_disable_phy/hic_dnt_io_clkgate/CP
                                                         CKLNQD8BWP12T35P140
                                                                           0.002     0.034      0.000     0.020     0.013   2        1.000
      data_slice_data_byte_disable/inst_hic_lp_clkgate_dfi_data_byte_disable_phy/hic_dnt_io_clkgate/Q
                                       CP ^ -> Q ^       CKLNQD8BWP12T35P140
                                                                           0.025     0.059      0.000     0.016     0.025            1.139
      clk_phy_dfi_data_byte_en__L1_I0/I
                                                         DCCKND12BWP12T35P140
                                                                           0.005     0.064      0.000     0.026     0.025   3        1.000
      clk_phy_dfi_data_byte_en__L1_I0/ZN
                                       I ^ -> ZN v       DCCKND12BWP12T35P140
                                                                           0.007     0.072      0.000     0.010     0.014            1.139
      clk_phy_dfi_data_byte_en__L2_I0/I
                                                         DCCKND16BWP12T35P140
                                                                           0.002     0.074      0.000     0.013     0.014   1        1.000
      clk_phy_dfi_data_byte_en__L2_I0/ZN
                                       I v -> ZN ^       DCCKND16BWP12T35P140
                                                                           0.008     0.082      0.000     0.009     0.026            1.139
      clk_phy_dfi_data_byte_en__L3_I1/I
                                                         DCCKND16BWP12T35P140
                                                                           0.002     0.085      0.000     0.012     0.026   2        1.000
      clk_phy_dfi_data_byte_en__L3_I1/ZN
                                       I ^ -> ZN v       DCCKND16BWP12T35P140
                                                                           0.007     0.092      0.000     0.007     0.022            1.139
      clk_phy_dfi_data_byte_en__L4_I1/I
                                                         DCCKND12BWP12T35P140
                                                                           0.001     0.093      0.000     0.010     0.022   2        1.000

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