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Symbolic Netlist to Innovus-friendly Netlist

 

run_lc_dc.csh

\rm lc_shell*.log
\rm dc_shell*.log

###############################
# 1 gen *.db by *.lib 
# for example, AND_OR_INV.db.
###############################

# get asap7nm/AND_OR_INV.db
lc_shell -64bit -f gen_AND_OR_INV_db.tcl > lc_shell_AND_OR_INV_db.log

###############################
# 2 syn symbolic netlist to Innovus-friendly *.v by *.db
###############################

# test simple circuit (MAJ1-INV-MAJ2 symbolic expression) netlist by AND_OR_INV.db
dc_shell -64bit -f MAJ1-INV-MAJ2_syn_AND_OR_INV_db.tcl > dc_shell_MAJ1-INV-MAJ2_syn_AND_OR_INV_db.log

gen_AND_OR_INV_db.tcl

read_lib asap7nm/asap7sc7p5t_24_INVBUF_LVT_FF_AND_OR_INV.lib

write_lib -output asap7nm/AND_OR_INV.db asap7sc7p5t_22b_INVBUF_LVT_FF_191110

exit

MAJ1-INV-MAJ2_syn_AND_OR_INV_db.tcl

set link_library { * asap7nm/AND_OR_INV.db }
set target_library asap7nm/AND_OR_INV.db

read_verilog { test.v }

current_design test_circuit
link

read_sdc aes.sdc

#ezp1110 compile_ultra -gate_clock

#ezp1110 report_timing -capacitance -significant_digits 6 > timing.report
#ezp1110 report_power > power.report
#ezp1110 report_area > area.report

uniquify
write -f verilog -o MAJ1-INV-MAJ2_syn_AND_OR_INV.v -hierarchy

exit

test.v

module test_circuit (clk, in1, in2, in3, in4, in5, out1);

input clk, in1, in2, in3, in4, in5;
output out1;
wire n0, n1;

assign n0 = (in1 & in2) | (in1 & in3) | (in2 & in3) ;
assign n1 = ~n0; 
assign out1 = (in4 & in5) | (in4 & n1) | (in5 & n1) ;

endmodule

aes.sdc

create_clock [get_ports {clk}] -name clk -period 2000

set_ideal_network [get_ports clk]

MAJ1-INV-MAJ2_syn_AND_OR_INV.v

/////////////////////////////////////////////////////////////
// Created by: Synopsys Design Compiler(R)
// Version : O-2018.06-SP5-3
// Date : Sun Nov 10 20:21:12 2019
/////////////////////////////////////////////////////////////


module test_circuit ( clk, in1, in2, in3, in4, in5, out1 );
input clk, in1, in2, in3, in4, in5;
output out1;
wire n0, n1, N0, N1, N2, N3, N4, N5, N6, N7;

GTECH_OR2 C9 ( .A(N2), .B(N3), .Z(n0) );
GTECH_OR2 C10 ( .A(N0), .B(N1), .Z(N2) );
GTECH_AND2 C11 ( .A(in1), .B(in2), .Z(N0) );
GTECH_AND2 C12 ( .A(in1), .B(in3), .Z(N1) );
GTECH_AND2 C13 ( .A(in2), .B(in3), .Z(N3) );
GTECH_NOT I_0 ( .A(n0), .Z(n1) );
GTECH_OR2 C15 ( .A(N6), .B(N7), .Z(out1) );
GTECH_OR2 C16 ( .A(N4), .B(N5), .Z(N6) );
GTECH_AND2 C17 ( .A(in4), .B(in5), .Z(N4) );
GTECH_AND2 C18 ( .A(in4), .B(n1), .Z(N5) );
GTECH_AND2 C19 ( .A(in5), .B(n1), .Z(N7) );
endmodule

lc_shell_AND_OR_INV_db.log

Library Compiler (TM)

Version J-2014.09 for RHEL64 -- Aug 12, 2014
Copyright (c) 1988-2014 Synopsys, Inc.

This software and the associated documentation are confidential and 
proprietary to Synopsys, Inc. Your use or disclosure of this software 
is subject to the terms and conditions of a written license agreement 
between you, or your company, and Synopsys, Inc.

Initializing...
#read_lib asap7nm/asap7sc7p5t_24_INVBUF_LVT_FF.lib
read_lib asap7nm/asap7sc7p5t_24_INVBUF_LVT_FF_AND_OR_INV.lib
Reading '/home/zpei/Majority-Gate/Innovus/innovus_sample/tech/asap7sc7p5t_24_INVBUF_LVT_FF_AND_OR_INV.lib' ...
Warning: Line 1, The 'default_inout_pin_cap' attribute is not specified. Using 1.00. (LBDB-172)
Warning: Line 1, The 'default_input_pin_cap' attribute is not specified. Using 1.00. (LBDB-172)
Warning: Line 242, Cell 'INVx1_ASAP7_75t_L', pin 'A', The pin 'A' does not have a internal_power group. (LBDB-607)
Warning: Line 77, Cell 'INVx1_ASAP7_75t_L', The cell_leakage_power attribute of the 'INVx1_ASAP7_75t_L' cell is redundant
and not used in the leakage_power modeling. (LBDB-644)
Warning: Line 255, Cell 'AND2x2_ASAP7_75t_L', The cell_leakage_power attribute of the 'AND2x2_ASAP7_75t_L' cell is redundant
and not used in the leakage_power modeling. (LBDB-644)
Warning: Line 646, Cell 'OR2x2_ASAP7_75t_L', The cell_leakage_power attribute of the 'OR2x2_ASAP7_75t_L' cell is redundant
and not used in the leakage_power modeling. (LBDB-644)
Warning: Line 1, The 'default_leakage_power_density' attribute is not specified. Using 0.00. (LBDB-172)
Technology library 'asap7sc7p5t_22b_INVBUF_LVT_FF_191110' read successfully
1
write_lib -output asap7nm/AND_OR_INV.db asap7sc7p5t_22b_INVBUF_LVT_FF_191110
Wrote the 'asap7sc7p5t_22b_INVBUF_LVT_FF_191110' library to '/home/zpei/Majority-Gate/Innovus/innovus_sample/asap7nm/AND_OR_INV.db' successfully
1
exit
Memory usage for this session 8 Mbytes.
CPU usage for this session 0 seconds ( 0.00 hours ).

Thank you...

dc_shell_MAJ1-INV-MAJ2_syn_AND_OR_INV_db.log

Design Compiler Graphical 
DC Ultra (TM)
DFTMAX (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)

Version O-2018.06-SP5-3 for linux64 - Jun 06, 2019

Copyright (c) 1988 - 2019 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited.
Initializing...
set link_library { * asap7nm/AND_OR_INV.db }
* asap7nm/AND_OR_INV.db 
set target_library asap7nm/AND_OR_INV.db
asap7nm/AND_OR_INV.db
#ezp1108 set link_library { * asap7nm/MAJFF_INVFF.db }
#ezp1108 set target_library asap7nm/MAJFF_INVFF.db
read_verilog { test.v }
Loading db file '/home/zpei/Majority-Gate/Innovus/innovus_sample/asap7nm/AND_OR_INV.db'
Loading db file '/usr/local/cad/synopsys/syn/O-2018.06-SP5-3/libraries/syn/gtech.db'
Loading db file '/usr/local/cad/synopsys/syn/O-2018.06-SP5-3/libraries/syn/standard.sldb'
Loading link library 'asap7sc7p5t_22b_INVBUF_LVT_FF_191110'
Loading link library 'gtech'
Loading verilog file '/home/zpei/Majority-Gate/Innovus/innovus_sample/test.v'
Detecting input file type automatically (-rtl or -netlist).
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/zpei/Majority-Gate/Innovus/innovus_sample/test.v
Presto compilation completed successfully.
Current design is now '/home/zpei/Majority-Gate/Innovus/innovus_sample/test_circuit.db:test_circuit'
Loaded 1 design.
Current design is 'test_circuit'.
test_circuit
current_design test_circuit
Current design is 'test_circuit'.
{test_circuit}
link

Linking design 'test_circuit'
Using the following designs and libraries:
--------------------------------------------------------------------------
test_circuit /home/zpei/Majority-Gate/Innovus/innovus_sample/test_circuit.db
asap7sc7p5t_22b_INVBUF_LVT_FF_191110 (library) /home/zpei/Majority-Gate/Innovus/innovus_sample/asap7nm/AND_OR_INV.db

1
read_sdc aes.sdc

Reading SDC version 2.1...
1
#ezp1110 compile_ultra -gate_clock
#ezp1110 report_timing -capacitance -significant_digits 6 > timing.report
#ezp1110 report_power > power.report
#ezp1110 report_area > area.report
uniquify
1
write -f verilog -o MAJ1-INV-MAJ2_syn_AND_OR_INV.v -hierarchy
Writing verilog file '/home/zpei/Majority-Gate/Innovus/innovus_sample/MAJ1-INV-MAJ2_syn_AND_OR_INV.v'.
1
exit

Thank you...

 

 

 

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