Protected: Why does inserting or removing buffers help fix timing violations?
February 23, 2025
There is no excerpt because this is a protected post.
There is no excerpt because this is a protected post.
Two primary checks are setup and hold checks. Once a clock is defined at clock pin of a flip-flop (FF), setup and hold checks are automatically inferred for the FF. Timing checks are generally performed at multiple conditions including worst-case slow condition and best-case fast condition. Typically, worst-case slow condition is critical for setup check… read more »
Turbodebug check Design netlist about clk div timing path: Fig. 1 Design/inst_clk_div Fig. 2, 3 Design/inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN Fig. 4 Design/inst_clk_div/inst_clk_div_dff/hic_dnt_out_reg/Q (constraint below create_generated_clock set it as RootPin, but design inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN as RootPin in CTS Spec file, as Fig. 4 Q pin (out_p) connects to Fig. 2 in0 actually) #Constraint create_clock [get_ports clk4x ] -name dummy_clk4x -period 0.5*0.833 -waveform… read more »
For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. http://www.techdesignforums.com/practice/guides/on-chip-variation-ocv/ For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915…. read more »
1. Which library files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib 2. Which files are about design? Netlist, constraint, IO file, scan def 3. What should be checked before APR? Check library files,… read more »