Configure STA environment

What’s STA environment? Specifying Clocks. Clock uncertainty and Clock latency Generated clocks Input paths constraint Output paths constraint  Timing path groups External attributes modeling  Check design rules Refine timing analysis Point-to-point specification Set up environment for static timing analysis. Specification of correct constraints is important in analyzing STA results. Design environment should be specified accurately… read more »

Path delay in cross clock domain

Sometimes, for cross clock domain timing analysis, incorrect timing report from mistake Path Delay due to big source clock paths latency/skew or target paths latency/skew would lead tool report and fix timing violation wrongly. Designer analysis launch clock paths latency/skew and capture clock paths latency/skew, find out which path(s) is/are too long, for example, it… read more »

same source create_generated_clock -add

#Constraint set CLK_PHASE_0_SRC “dummy_clk4x” set EDGES {1 3 5} set CLK_PHY_PORT “clk4x” set PERIOD [expr 0.833 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] set PHY_CLK_PERIOD $PERIOD set PHY_HALF [expr 0.5 * $PHY_CLK_PERIOD] set PHY_QUARTER [expr 0.25 * $PHY_CLK_PERIOD] set CTLR_CLK_PERIOD [expr 2 * $PHY_CLK_PERIOD] set PHY_DDL_CLK_PERIOD [expr 0.2 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] create_clock [get_ports $CLK_PHY_PORT ] -name dummy_clk4x… read more »

Clock Tree Latency Skew Uncertainty

Clock to a SoC/chip is like blood to a dog body. If you want the pet smart and strong, hematological system would be healthy. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the chip…. read more »

CTS Spec UnsyncPin RootPin based on Constraint and Netlist

Turbodebug check Design netlist about clock timing path: Fig. 1 Design/inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux #Constraint create_clock -name clk_ddl_test_fdbk [get_pin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/$NEG_OUTPUT ] -period $PHY_DDL_SCALED_CLK_PERIOD -waveform “0 $PHY_DDL_SCALED_HALF” #CTS Spec file #Excluded Output pin due to create_clock inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN GlobalUnsyncPin +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand0/hic_dnt_nand2/A1 +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand1/hic_dnt_nand2/A1 #—————————————————- # Clock Name : clk_ddl_test_fdbk #—————————————————- AutoCTSRootPin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN  

Clock divider and CTS

Turbodebug check Design netlist about clk div timing path: Fig. 1 Design/inst_clk_div Fig. 2, 3 Design/inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN Fig. 4 Design/inst_clk_div/inst_clk_div_dff/hic_dnt_out_reg/Q (constraint below create_generated_clock set it as RootPin, but design inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN as RootPin in CTS Spec file, as Fig. 4 Q pin (out_p) connects to Fig. 2 in0 actually) #Constraint create_clock [get_ports clk4x ] -name dummy_clk4x -period 0.5*0.833 -waveform… read more »


Sometimes, it is necessary to add constraint, such as set_disable_timing to let tool ignore timing path which should not be checked, critical path would be fixed by tool correctly. set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_master/delay_0] set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_clk_wr/delay_0] #ezp set_disable_timing -from in1 -to pass [get_cells dll_delay_line/delay_0] #ezp set_disable_timing -from in1… read more »

meet skew via constraint

setOptMode -ignorePathGroupsForHold {in2reg reg2reg in2out} -holdTargetSlack 0 -setupTargetSlack 0 -fixHoldAllowSetupTnsDegrade false setOptMode -holdFixingCells {BUFFER_NAME} setDelayCalMode -engine xxx -SIAware true -signoff true set_analysis_view -setup funcPostC_PVT_setup  -hold funcPostC_PVT_setup update_constraint_mode -name funcPostC -sdc_files “constraint_file_path” optDesign -postRoute -outDir ./rpts/fix_skew_setup update_constraint_mode -name funcPostC -sdc_files “constraint_file_path” setOptMode -fixHoldAllowSetupTnsDegrade true optDesign -postRoute -hold -outDir ./rpts/fix_skew_hold constraint file set DQS_TSEL_SEL {tsel_dqs_1_opad tsel_dqs_2_opad tsel_dqs_3_opad}… read more »

update clock latency

Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »

Prepare files and check netlist

1. Which library files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib 2. Which files are about design? Netlist, constraint, IO file, scan def 3. What should be checked before APR? Check library files,… read more »