Menu

    Blog Stats

    • 134,102 hits

Design

Symbolic Netlist to Innovus-friendly Netlist

July 12, 2024

  run_lc_dc.csh \rm lc_shell*.log \rm dc_shell*.log ############################### # 1 gen *.db by *.lib # for example, AND_OR_INV.db. ############################### # get asap7nm/AND_OR_INV.db lc_shell -64bit -f gen_AND_OR_INV_db.tcl > lc_shell_AND_OR_INV_db.log ############################### # 2 syn symbolic netlist to Innovus-friendly *.v by *.db ############################### # test simple circuit (MAJ1-INV-MAJ2 symbolic expression) netlist by AND_OR_INV.db dc_shell -64bit -f MAJ1-INV-MAJ2_syn_AND_OR_INV_db.tcl > dc_shell_MAJ1-INV-MAJ2_syn_AND_OR_INV_db.log… read more »

Configure STA environment

April 14, 2019

What’s STA environment? Specifying Clocks. Clock uncertainty and Clock latency Generated clocks Input paths constraint Output paths constraint  Timing path groups External attributes modeling  Check design rules Refine timing analysis Point-to-point specification Set up environment for static timing analysis. Specification of correct constraints is important in analyzing STA results. Design environment should be specified accurately… read more »

Modeling Power Terminology

April 14, 2019

The power a circuit dissipates falls into two broad categories: Static power Dynamic power Static Power Static power is the power dissipated by a gate when it is not switching – that is, when it is inactive or static. Static power is dissipated in several ways. The largest percentage of static power results from source-to-drain… read more »

Path delay in cross clock domain

October 2, 2015

Sometimes, for cross clock domain timing analysis, incorrect timing report from mistake Path Delay due to big source clock paths latency/skew or target paths latency/skew would lead tool report and fix timing violation wrongly. Designer analysis launch clock paths latency/skew and capture clock paths latency/skew, find out which path(s) is/are too long, for example, it… read more »

same source create_generated_clock -add

April 14, 2019

#Constraint set CLK_PHASE_0_SRC “dummy_clk4x” set EDGES {1 3 5} set CLK_PHY_PORT “clk4x” set PERIOD [expr 0.833 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] set PHY_CLK_PERIOD $PERIOD set PHY_HALF [expr 0.5 * $PHY_CLK_PERIOD] set PHY_QUARTER [expr 0.25 * $PHY_CLK_PERIOD] set CTLR_CLK_PERIOD [expr 2 * $PHY_CLK_PERIOD] set PHY_DDL_CLK_PERIOD [expr 0.2 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] create_clock [get_ports $CLK_PHY_PORT ] -name dummy_clk4x… read more »

CTS Spec UnsyncPin RootPin based on Constraint and Netlist

April 14, 2019

Turbodebug check Design netlist about clock timing path: Fig. 1 Design/inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux #Constraint create_clock -name clk_ddl_test_fdbk [get_pin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/$NEG_OUTPUT ] -period $PHY_DDL_SCALED_CLK_PERIOD -waveform “0 $PHY_DDL_SCALED_HALF” #CTS Spec file #Excluded Output pin due to create_clock inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN GlobalUnsyncPin +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand0/hic_dnt_nand2/A1 +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand1/hic_dnt_nand2/A1 #—————————————————- # Clock Name : clk_ddl_test_fdbk #—————————————————- AutoCTSRootPin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN  

Clock divider and CTS

April 14, 2019

Turbodebug check Design netlist about clk div timing path: Fig. 1 Design/inst_clk_div Fig. 2, 3 Design/inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN Fig. 4 Design/inst_clk_div/inst_clk_div_dff/hic_dnt_out_reg/Q (constraint below create_generated_clock set it as RootPin, but design inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN as RootPin in CTS Spec file, as Fig. 4 Q pin (out_p) connects to Fig. 2 in0 actually) #Constraint create_clock [get_ports clk4x ] -name dummy_clk4x -period 0.5*0.833 -waveform… read more »

design flow simple

July 10, 2015

Simplify a general design flow post-floorplan should be: 1st timing driven placement according to constraints, skew/latency was considered as ‘ideal’ zero, optDesign –preCTS. 2nd CTS, optDesign –postCTS. Clock tree have insertion or propagation delay after CTS. 3rd routing, optDesign –postRoute, optDesign –hold -postRoute. Usually, fix setup violation first, then hold violation in order to obtain… read more »

Clock Tree Synthesis

April 14, 2019

In clock tree synthesis, do ONE thing only, insert CLK INV (NOT CKBUFF !) which could fix rising and falling transition/duty, to min clock tree latency and skew, balance sink/leaf pins which should be balanced, don’t balance pins which should not be balanced. CTS Macro Model Let tool know the segment of clock path latency which… read more »

set_disable_timing

April 14, 2019

Sometimes, it is necessary to add constraint, such as set_disable_timing to let tool ignore timing path which should not be checked, critical path would be fixed by tool correctly. set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_master/delay_0] set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_clk_wr/delay_0] #ezp set_disable_timing -from in1 -to pass [get_cells dll_delay_line/delay_0] #ezp set_disable_timing -from in1… read more »

Older Entries »
Sidebar