IntSim: A CAD tool for Optimization of Multilevel Interconnect Networks

Intsim: A CAD Tool for Optimization of Multilevel Interconnect Networks

Download IntSim: http://www.monolithic3d.com/simulators.html

Download: IntSim Algorithm and Equations

这篇论文主要介绍了IntSim的工作原理和方法论以及案例。IntSim是一款主要用于优化半导体电路中多层互连网络的电脑辅助设计工具。

从宏观角度看，该论文主要内容大致包括2 + 4 个模型，或者说论文按IntSim算法中涉及到的数据处理以及数据流顺序主要分 2 + 4 + 1 部分（当然工具应用方面有3个案例可以用来验证其正确性，可靠性和实用性）：

推导出一个新的随机线长分布的模型；这个模型新颖就在于其前提假设芯片上的若干电路区块中（论文中可能定义其为：socket，窝）有逻辑门的可能性是不确定的，换句话说，逻辑门是随机分布，而不是均匀分布在芯片上，其概率等于逻辑门与芯片面积的比值。后面我会有具体说明。这里有个很有趣的事情：与以往的线分布模型不同，新的随机线长分布模型是关于逻辑门尺寸的函数，本质上，如果芯片的面积固定了，我们用更小尺寸的逻辑门，它们能放得更近，所以平均线长减小。实际的算法流程是先根据芯片的工作频率选逻辑门尺寸，再根据逻辑门尺寸推导出随机线长分布，从而从底层到上层bottom-up（也就是tape-out工艺顺序）依次优化1.本地互连，2.中间/半全局互连（或者叫没加Repeater）互连，3.全局互连，4.插上Repeater后的互连，计算功耗，再把这些互连用算法组合起来。
描述如何根据芯片的工作频率时序或其他要求选逻辑门尺寸；可参考公式(12) $\begin{align*} t_d &= \frac{1-{\color{Blue} margin\ (fraction\ of\ a\ clock\ cycle\ that\ constitutes\ skew\ and\ variability)}}{f} \\ &=L_d0.7\frac{R_{NAND}}{{\color{Red} W}}\left (f.o.C_{NAND}{\color{Red} W} +f.o.\chi \cdot {\color{Magenta} k_l (7.3+W)^{1-p}} \right ) \end{align*}$
优化本地互连；
中间/半全局（或者叫没加Repeater）互连；
全局互连；
插上Repeater后的互连；
把前面涉及到的几个模型（并计算功耗）用算法组合起来。

从微观角度看，论文中主要模型中涉及到需要处理和计算的物理量或者半导体工业界特征（指标）有相关的公式推导或者文献参考。

本文将主要分析IntSim的模型涉及到的基础理论和算法，大体按照论文顺序先从各个模型开始分析，最后基于论文和MonolithIC 3D公司在线文档介绍分析组合算法。

Models used in IntSim v2.0

http://www.monolithic3d.com/intsims-models.html

The Models from the Paper

Notation for the Paper

N_sockets: the number of gate sockets.

N_gates: the number of gates.

p_gates_:the percentage of die area that is occupied by logic gates.

$l$ : a certain length for interconnect, value of l is in gate socket lengths. 互连长度值以门窝长度表示。比如，两个门窝之间隔着3个门窝，则l的值为4。

$M(l)$ : the number of gate socket pairs separated by a distance l.

$I_{exp}(l)$ : the average number of interconnects between a gate socket pair separated by l.

$i(l)$ : the expected number of interconnects of a certain length l.

P(gate in block A) = p_gates: 门窝A有逻辑门的概率，也是逻辑门在芯片上的面积占比。

f.o.: fan-out，系统的平均扇出数，一个gate后面驱动gate或ff, reg的个数。

$\alpha = \frac{f.o.}{f.o.+1}$

k : Rent’s constant

p : Rent’s constant

N_A: the number of gates in block A

N_B: the number of gates in block B

N_C: the number of gates in block C

L_avg: 平均线长

t_d: the delay of a logic path having 2 input NAND gates driving a fan-out f.o.

L_d: logic depth

$\chi = \frac{4}{f.o.+3}$ : a factor, convert point-to-point net length to wiring net length

R_NAND: average drive resistance of a minimum size 2 input NAND gate, obtained from equations given in [18]

_CNAND: input capacitance of the NAND gate, computed nMOS and pMOS devices are sized equally in a 2 input NAND gate

_Cint: capacitance of an average wire

c: capacitance per unit length of a wire

A: die area

F: feature size

W: width

$k_l=c\cdot \sqrt A \cdot \left ( \frac{20.4F^2}{A} \right )^{1-p}\left (\frac{p+1-4^{p-0.5}}{2(p-0.5)(p+0.5)p} \right )$

P : global wire pitch

N_{power_pads}: the number of power pads

$\rho$ : wire resistivity

$I_T$ : current distributed per pad

d_{pad_to_pad}: distance between adjacent power pads

e_router: routing efficiency factor

V_IR : user specified IR drop lime for global power wiring

l_pad : pad length

D : distance between the drive and load of a H tree

R_o : output resistance of a minimum size inverter

C_o : input capacitance of a minimum size inverter

$\beta _o$ : raio of maximum rise time allowed for clock tree to the clock period

f : clock frequency

c_clock : clock wire capacitance per unit length

P_local: local interconnect pitch, 2F

F : feature size

l_max : the length of the longest wire routed in local interconnect levels

e_W: wiring efficiency，绕线效率

e_router : the efficiency of the wire routing tool (typically around 0.5)

e_power/gnd : fraction of area used by power and ground wires, obtained from the model for local power distribution networks derived in [20].

e_vias : fraction of area used by vias

N_{wire_higher} : the number of wires routed in higher metal levels

N_repeaters : the number of repeater for higher metal levels

$\lambda$ : design rule unit

s : via covering factor which is typically 3 [12]

N_{wires_higher}: found from the stochastic wiring distribution by finding the number of wires whose length is greater than l_max

$\rho$ : wire resistivity, ( $\Omega \cdot m$ )

C : wire capacitance per unit length (F/m)

b : percentage of time circuit is not sleep gated

f : frequency (Hz)

R_o : resistance of minimum sized repeater ( $\Omega$ )

C_o : capacitance of minimum sized repeater (F)

I_leak : leakage of minimum sized repeater (A)

V_dd : supply voltage (V)

$\beta$ : 0.25 (short wires) 0.9 (longer wires)

a : activity

ar : Wire aspect ratio

[18] Models in BACPAC: www.eecs.umich.edu/~dennis/bacpac

[20] R. Sarvari, A. Naeemi, P. Zarkesh-Ha, J. Meindl, “Design and optimization for nanoscale power distribution networks in gigascale systems”, Proc. Intl. Interconnect Technology conference, 2007

[12] Q. Chen, J. Davis, P. Zarkesh-Ha, J. Meindl, “A compact physical via blockage model”, Trans. VLSI Systems, Dec. 2000

1. Derivation of Stochastic Wiring Distribution

– A New Stochastic Wire Length Distribution Model

The new wire length distribution considers random arrangement of gates in a circuit block rather than assuming gates are uniformly distributed all over the chip and then finds a distribution of wire lengths using Rent’s rule.

在这篇论文发表前的人们使用Rent法则研究线长的分布情况是假设芯片上的门都是均匀分布，而论文中这种新的线长分布考虑在一个电路区块中的门是随机分布的。打个不恰当的比方：一个萝卜一个坑，但是一个坑不一定有一个萝卜，比如：菜地里有10 x 10 = 100个坑，这些坑里总共随机长了30个萝卜，那么每个坑里有萝卜的概率是30%。需要注意的是socket一个门窝中可能不止一个逻辑门。（根据公式 7 : N_A= 1，是否说明block = socket，一个socket最多只能有一个逻辑门，或者一个block可以有多个逻辑门？）

Define a new quantity called a gate socket. 假设芯片的形状是正方形。

定义了一个新的量：门窝，我把这个量翻译成“门窝”，因为“窝”的含义可能更贴切socket在论文中的含义，为了方便理解并熟记该术语从而在原理上更深刻地理解优化多层互连网络的方法论，我们不妨这样理解：窝从字形上：某个窝，也就是某个“穴内”，有个填空，这就对应于芯片上，某“物理位置”，可能有“逻辑门”，也有可能没“逻辑门”，门窝有逻辑门的概率等于芯片上逻辑门的面积占比，所以，比较形象的说明了下图1。那么门的个数，门窝个数，逻辑门与芯片占比的关系如下：

N_gates= N_sockets• p_gates (1)

门的数量 = 门窝数量 x 芯片上逻辑门的面积占比

例如：

10M 门 = 门窝数量 x 50%

得：门窝数量是20M。并且10M门随机分布在这些门窝里。如果门窝数不是整数，则结果四舍五入取整数。

The expected number of interconnects of a certain length l:

$i(l)=M(l)\cdot I_{exp}(l)$ (2)

某长度的互连的期望条数 = 该长度分隔的门窝对数量 x 该长度分隔的介于一个门窝对之间的互连的平均条数（2）

可以这样理解，互连长度可能取值范围是(0, ∞)，每个值都有对于的N条互连，比如我们想求出长度为10μm的互连的期望条数，那么我们可以将10μm分隔的门窝对数量，比如5对门窝，乘以一个网窝对之间的互连的平均条数，假设平均6条互连，等于30条，那么意味着长度为10微米的期望互连条数有30条。

M(l) = f (l, N_sockets) (3)

[16] J. Davis, V. De, J. Meindl, “Apriori wiring estimations and optimal multilevel wiring networks for portable ULSI systems”, Proc. Electronic Components and Technology Conference, 1996

与Davis[16]推导以线长l分隔的逻辑门对个数的方法类似，求门窝对个数的函数是一个以互连长度和门窝个数为自变量的分段函数，区间分别是：大于等于1小于芯片边长（即两个门窝分布在芯片分布在芯片内部），大于等于边长小于2倍边长（两个门窝可能分布在芯片四边中的某边的一头一尾或者对角顶点上，即它们分布在芯片的边缘）。在此不写具体公式。其实很好理解，直观理解门窝对个数由互连长度和门窝个数决定，在其他条件不变的情况下，当门窝个数越多即芯片越大，门窝对个数越多；其他条件不变的情况下，当互连长度越小，门窝对个数越多。

A gate socket length is defined as the distance between two adjacent gate sockets and is equal to $\left (\frac{S_{die}}{N_{sockets}} \right )^{0.5}$ , Davis defines gate pitch as $\left (\frac{S_{die}}{N_{gates}} \right )^{0.5}$ , so a socket length = $\left (\frac{N_{gates}}{N_{sockets}} \right )^{0.5}=p_{gates}^{0.5}$ . 也就是说，因为定义门窝的长度是两个相邻门窝的距离，Davis定义门间距是两个门之间的距离，所以一个门窝长度就是“门窝有门”的概率的开平方。

以图1为例，互连距离为4的门窝对，A-C，求这个互连的平均个数：

$I_{exp}=P(gate\ in\ block\ A)\cdot \frac{I_{A-to-C}}{N_C}$ (4)

$P(gate\ in\ block\ A)=\frac{N_{gates}}{N_{sockets}}=p_{gates}$ (5)

巧妙就巧妙在，把门窝的个数简化理解为对应的线长值，换句话说，将线长与门窝个数“统一”起来，方便理解且大大降低计算量。好比说一个萝卜一个坑，但是一个坑不一定一个萝卜，比如菜地里有10 x 10 = 100个坑，这些坑里总共随机长了30个萝卜，那么每个坑里有萝卜的概率是30%，而且每个萝卜是随机分布在不同的坑里。萝卜对A和C的距离以坑的尺寸值为单位，比如A坑到C坑的距离为5，即这两个萝卜中间隔了4个坑。需要注意的是socket一个门窝中可能不止一个逻辑门。

$I_{A-to-C}=\alpha k\left [ \left ( N_A +N_C \right )^P\right -N_B^P + \left ( N_B+N_C \right )^P -\left ( N_A+N_B+N_C \right )^P]$ (6)

$\begin{align*} N_A &=1 \\ N_B &=p_{gates}l(l-1) \\ N_C &=2p_{gates}l \\ \end{align*}$ (7)

Combining (2-7) and normalizing, we get the average number of interconnects of length l gate socket lengths (是不是理解成以l个门窝或门窝个数度量互连长度或者？) to be:

The average wire length for this interconnect distribution is

$\begin{align*} L_{avg}(in\ gate\ socket\ lengths) &=\frac{\int_{1}^{2\sqrt{N_{sockets}}}li(l)dl}{\int_{1}^{2\sqrt{N_{sockets}}}i(l)dl} \\ &= \frac{\left [ \frac{p-0.5}{p}-\sqrt{N_{sockets}}-\frac{p-0.5}{6\sqrt{N_{sockets}}(p+0.5)}+N_{sockets}^p \left (\frac{-p-1+4^{p-0.5})}{2(p+0.5)p(p-1)} \right )\right]}{\left ( -N_{sockets}^p \frac{1+2p-2^{2p-1}}{p(p-1)(2p-1)(2p-3)} -\frac{1}{6p} -\frac{2\sqrt{N_{sockets}}}{2p-1} -\frac{N_{sockets}}{p-1} \right )} \end{align*}$

求互连分布的平均线长，等于，总线长除以线的个数，也就是各个长度对应的线长与各自长度对应的线的个数相乘再求和，最后除以线的总个数。

因为线的个数是以线长为自变量的函数，所以积分下上限分别是从位于芯片内部相邻的两个区块的线长（最短的线长，也就是一个门窝的长度，记为1）到位于芯片边缘对角顶点的两个区块的线长（最长的线长，也就是芯片边长的2倍）。

For a large number of gates and p>0.5, this expression can be simplified to

$L_{avg}(in\ gate\ pitches)={\color{Magenta} p_{gates}^{1-p}}N_{gates}^{p-0.5}\left (\frac{p+1-4^{p-0.5}}{2(p-0.5)(p+0.5)p} \right )$ (9)

When gates were uniformly distributed over the die area, Davis derived the expression for average wire length to be

$L_{avg}(in\ gate\ pitches)=N_{gates}^{p-0.5}\left (\frac{p+1-4^{p-0.5}}{2(p-0.5)(p+0.5)p} \right )$

对比上面两个公式，可以发现，很明显，新的线分布情况下平均线长是近似化的Davis平均线长乘以一个因数：这个因数有关Rent常数p和逻辑门占芯片总面积的比例。在大部分经典的电路区块中，逻辑门占总芯片面积的50-75%。

图3对比了22 ISCA’89电路区块的平均线长测量值与Donath分布[18]的预测值，Davis分布的预测值，还有新的分布的预测值。Donath分布有75%的平均误差，Davis分布有38%的平均误差，新模型只有8%-24%的误差，对应于Rent常数p_gates范围(0.5-0.75)。

很明显，用新模型预测平均线长比Donath分布模型和Davis分布模型更精确。

从上表2，对比看Davis分布模型与新模型得到的平均线长。在Davis分布模型中标准电路Benchmark circuit里平均误差是26%，而新模型的平均误差只有2%-12%。

很明显，用新模型预测平均线长比Davis分布模型更精确。

图4表明对于有12M逻辑门的36mm² 电路区块，逻辑门占芯片面积比例为0.5，p_gates = 0.5，平均扇出数为3，fan-out = 3，Rent’s constant k=4, p=0.55。新的线分布与Davis线分布的区别。公式8和9表明新模型的平均长度比Davis分布模型少27%，从图4b，线性尺度表明线长越短，线长分别的差别越大。

[18] Models in BACPAC: www.eecs.umich.edu/~dennis/bacpac

2. Logic Gate Modeling

Logic gate paths are modeled as multiple stages of 2-input NAND gates between flip-flops, as shown in Fig. M4: Logic path model.

$t_d=L_d0.7\frac{R_{NAND}}{W}\left (f.o.C_{NAND}W +f.o.\chi C_{int} \right )$ (10)

$\begin{align*} C_{int}={\color{green} c}\cdot L_{avg}&={\color{Green} c}\cdot{\color{Magenta} p_{gates}^{1-p}}N_{gates}^{p-0.5}\left (\frac{p+1-4^{p-0.5}}{2(p-0.5)(p+0.5)p} \right ){\color{Blue} \left (\frac{A}{N_{gates}} \right )^{0.5}} \\ &={\color{green}c} \cdot \left(\frac{20.4(7.3+W)F^2}{A} \right )^{1-p}\left (\frac{p+1-4^{p-0.5}}{2(p-0.5)(p+0.5)p} \right ) \sqrt{A} \end{align*} \\ A_{NAND}=20.4(7.3+W)F^2 \ \ paper [8]$

[8] R. Venkatesan, J. Davis, et al., “Optimal n tier multilevel interconnect architectures for GSI”, Trans. VLSI Systems, Dec 2001

这里有个很有趣的事情：与前面的线分布模型不同，新的线分布是逻辑门尺寸的函数，本质上，如果芯片的面积固定了，我们用更小尺寸的逻辑门，它们能放得更近，所以平均线长减小。

$t_d=L_d0.7\frac{R_{NAND}}{W}\left (f.o.C_{NAND}W +f.o.\chi C_{int} \right )$ (10)

becomes

$t_d=L_d0.7\frac{R_{NAND}}{W}\left (f.o.C_{NAND}W +f.o.\chi \cdot {\color{Magenta} k_l (7.3+W)^{1-p}} \right )$ (12)

$\begin{align*} t_d &= \frac{1-margin\ (fraction\ of\ a\ clock\ cycle\ that\ constitutes\ skew\ and\ variability)}{f} \\ &=L_d0.7\frac{R_{NAND}}{W}\left (f.o.C_{NAND}W +f.o.\chi \cdot {\color{Magenta} k_l (7.3+W)^{1-p}} \right ) \end{align*}$

3. Global Interconnect Modeling

Please refer to the notation and Figure 5 about parameters in Equation 13.

4. Local Interconnect Modeling

IntSim has two wire levels for routing local signal, power and clock wiring.

${\color{Blue} 2e_wA} = {\color{Red} \chi P_{local} \sqrt{\frac{A}{N_{sockets}}} \int_{1}^{l_{max}} l\cdot i(l)dl} \\ where\\ {\color{Blue} e_w = 1-e_{router}-e_{power/gnd}-e_{vias}}$ (14)(15)

本质上，公式14的左边代表2层本地互连可用的绕线的区域的面积，右边是用来绕所有长度（从1到l_max门窝长度）的需要的区域的面积。

${\color{Blue} e_{vias} = \sqrt{\frac{(2N_{wires_higher}+2N_{repeaters})\cdot (P_{local}+s\lambda)^2}{A}}}$ (16)

请参考Notation中有关公式里各个参数的定义。

5. Intermediate and Semi-global Interconnect Modeling

中间和半全局互连建模基于公式(17)(18)。

${\color{Blue} 2e_wA} = {\color{Red} \chi P \sqrt{\frac{A}{N_{sockets}}} \int_{l_{min}}^{l_{max}} l\cdot i(l)dl} \\ where\\ {\color{Blue} e_w = 1-e_{router}-e_{power/gnd}-e_{vias}}$ (17)

公式(17)的左边代表2层互连可用的绕线的区域的面积，右边是用来绕线长度处于门窝长度一对线级之间从l_min 到l_max的需要的区域的面积。

P : the pitch of the pair of wiring levels.

Equation (18) 代表情况：在一对金属级的最长的线应该是时钟周期的一部分，参考[8]

${\color{Blue} \tau _{rc}=4.4\frac{\rho (P, AR) }{ar\cdot P^2}\cdot c\cdot l_{max}^2 \sqrt {\frac{A}{N_{sockets}}}=\frac{\beta}{f}}$ (18a)

公式 18a 表示没有插repeaters。No repeaters are inserted

${\color{Red} \tau_{rc}=\sqrt{\frac{A}{N_{sockets}}}\frac{2l_{max}\sqrt{\rho(P,ar)c\cdot R_o\cdot C_o}}{ar\cdot P} \left ( \frac{0.7}{\delta } +0.7\gamma +0.7\delta \right ) = \frac{\beta}{f}}$ (18b)

$\gamma = (0.73+0.07ln\phi_{gate} )^2 ,\ \theta = (0.88+0.07ln\phi_{gate})^2\\ where\\ \phi_{gate}=\frac{\frac{1}{2}a \cdot C_o\cdot V_{dd}^2 \cdot f}{\frac{1}{2} a\cdot C_o\cdot V_{dd}^2\cdot f + b\cdot V_{dd}\cdot I_{leak}}$

公式18b用于电路中插了repeater的阶段，需要考虑Energy-Delay Product minimization strategy[4]. Width of wires is equal to spacing between wires.线宽等于线之间的间距。

$\rho$ : wire resistivity, ( $\Omega \cdot m$ )

C : wire capacitance per unit length (F/m)

b: percentage of time circuit is not sleep gated

f : frequency (Hz)

R_o : resistance of minimum sized repeater ( $\Omega$ )

C_o : capacitance of minimum sized repeater (F)

I_leak : leakage of minimum sized repeater (A)

V_dd : supply voltage (V)

$\beta$ : 0.25 (short wires) 0.9 (longer wires)

a : activity

ar : Wire aspect ratio

中间和半全局级绕线效率有三个影响因素

Repeater 孔禁区因为repeater在更高的金属层
对于信号线在更高金属层的孔禁区，以[12]建模
电源/地孔禁区，在文献[20]有说明。

The wiring efficiency factor for intermediate and semi-global levels has three sources: (i) Repeater via blockage due to repeaters in higher metal levels (ii) Via blockage to signal wires routed in higher levels that is modeled based on [12] (iii) Power/ground via blockage that is got from equations in [20]. Wire resistivity increases due to size effects are modeled as shown in [21].

[8] R. Venkatesan, J. Davis, et al., “Optimal n tier multilevel interconnect architectures for GSI”, Trans. VLSI Systems, Dec 2001

[4] D. Sekar, R. Venkatesan, K. Bowman, et al, “Optimal repeaters for sub-50nm interconnect networks”, Proc. Intl. Interconnect Technology Conference, 2006

[12] Q. Chen, J. Davis, P. Zarkesh-Ha, J. Meindl, “A compact physical via blockage model”, Trans. VLSI Systems, Dec. 2000

[21] W. Steinhogl, G. Schindler, et al, “Comprehensive Study of the Resistivity of Copper Wires With Lateral Dimensions of 100 nm and Smaller,” J. of Applied Physics, 2005.

6. Algorithm to Combine All the Models and Design a 2D or 3D-IC

The key challenge with combining all the models shown thus far is:

The design of power interconnects and their area allocation depends on the chip power. However, chip power is not known until repeaters are designed in the multilevel wiring network, especially in sub-90nm chips where repeaters consume a significant fraction of total power.
Design of the interconnect stack needs some knowledge of via blockage caused by repeaters.

Thus, an iterative process is followed for assigning wires in a multilevel wiring network. Steps involved in simulating the 2D or 3D-IC are:

In IntSim, the process of selecting wire pitches for different interconnect levels proceeds in several steps:

Input all parameters: The user inputs various details of the system that is being modeled.
Logic gate sizing: Logic gates are sized based on Equation (12) such that clock frequency targets are reached.Margin: Fraction of clock cycle lost due to skew and process variations
For computing logic gate size W, if W becomes smaller, length becomes shorter, frequency decrease.Logic gate paths are modeled as multiple stages of 2-input NAND gates between flip-flops, as shown in Fig. M4: Logic path model. An average length wire, whose length is determined from the wire length distribution model, exists between two NAND gate stages. NAND gate sizes are determined based on these conditions, using the equations shown in Fig. M5: Equations for determining average gate size. While this is an approximate method to obtain logic gate sizes, area and power, it is simple and widely-used and is therefore adopted for IntSim v2.0. Please see [15][18] for more details of this model.
Generation of stochastic wiring distribution: Based on logic gate size chosen in Step 2, the fraction of die area occupied by logic gates, p_gates, is found. This is used to generate the stochastic wiring distribution given in Equation (8). The IntSim CAD tool relies on predicting the distribution of wire lengths on a chip, and using these for determining gate sizes and multilevel interconnect networks. The value of Rent’s constants k and p are determined from previous generations of a certain chip. For example, various generations of the Intel Pentium chips, such as the Pentium, Pentium Pro and the Pentium 4, all had similar Rent’s constants [17][18]. It is generally accepted that custom chips such as microprocessors have Rent’s constant p = 0.55 while standard-cell ASICs have Rent’s constant p = 0.65 [31], although there may be variations on a case-by-case basis. Rent’s constant k is typically around 4.
Set baseline parameters for iterations: The design of power interconnects and allocation of area for them depends on the chip power. However, chip power is not known until repeaters are designed in the multilevel wiring network, especially in sub-90nm chips where repeaters consume a significant fraction of total power. Also, design of the interconnect stack needs some knowledge of via blockage caused by repeaters. Thus, an iterative process is followed for assigning wires in a multilevel wiring network. An initial chip power estimate is set (as 100W, say) and the number of repeaters is set as 0.
Local interconnect modeling: Local wire pitch is set as 2F. Using Equations (14), (15) and (16), the longest wire routed in M1 and M2 is determined.公式14可以算出本地互连的最长的信号线IntSim v2.0 has two metal levels for each device layer to route local signal, power and clock interconnect networks. These metal levels are also designed to remove heat from transistors in stacked device layers. Local interconnect pitch is selected as 2F, where F is the minimum feature size. Length of the longest signal wire routed in local interconnect levels is obtained from the equations shown in Fig. M11. Power wire efficiency is obtained from the local power grid model derived in [26] and also from considerations shown in the thermal models page. Via blockage to higher metal levels and via blockage due to repeaters are modeled using equations derived in [27].
Arrangement of wires without repeaters: Once the longest wire routed in M1/M2 is determined, it is set as l_min in Equation (17)一旦步骤5本地互连的最长线长确定，即是公式17中的积分下限. Equations (17) and (18a) are then used to find the pitch of M3/M4 and and maximum wire length routed in them. This in turn is set as l_min for the next pair of metal levels and this process continues till the longest interconnect of the wiring distribution is assigned a pitch.
Intermediate and Semi-Global Interconnect Model（这步也称为“没有加repeater”的线布局阶段）
A 2D-IC, or each device layer of a 3D-IC, in IntSim v2.0 has its own set of intermediate and semi-global interconnects. The wire pitches of these interconnect levels are obtained using the equations shown in Fig. M12. Essentially, The right hand side of Eq. (1) denotes the area required for routing wires in a pair of wire levels, 公式（1）的右边是绕线的要求面积and the left hand side denotes the area available for routing，公式（1）的左边是绕线的可用面积. Here, P is the pitch of the pair of wiring levels. Eq. (2) and Eq. (3) represent the condition that the delay of the longest wire in a pair of metal levels should be a certain fraction of the clock period, as discussed in [24]. For short-wires whose delay is typically logic gate dominated, this fraction is set as 0.25, and for long-wires whose delay is wire dominated, this fraction is typically around 0.8-0.9. Eq. (2) represents this criterion when no repeaters are inserted while Eq. (3) represents the case when repeaters are inserted with the Energy-Delay Product minimization strategy discussed in the repeater models section. Width of wires is equal to spacing between wires.

The wiring efficiency factor for intermediate and semi-global levels has two sources. The first source is via blockage due to vias to higher levels of metal and due to repeaters. These are modeled based on [27]. The second source is power via blockage that is modeled based on [26]. Wire resistivity increases due to size effects are modeled as shown in [26].
Global interconnect modeling: A top-down process of global interconnect pitch selection and repeater insertion then begins. Global wire pitch is constrained to be the value found from Equation (13). The area needed for routing power wires is then found from equations given in [13], and this helps calculate the area available for signal wires in global wire levels. Clock wire area is neglected in IntSim because previous work has shown it is small [22]. Repeaters are inserted into these global signal wires, and the shortest signal wire routed in global wire levels is found based on a formula similar to Equation (17).
Assignment of wires with repeaters: Based on the length of shortest global signal wire, wires with repeaters are assigned to the pair of metal levels below the global wire levels based on Equations (17) and (18b). The pitch and shortest wire lmin are found for this pair of wiring levels and this l_min is set as l_max for the pair of wiring layers below it. Repeater insertion is performed for the pair of wiring layers below it and this keeps continuing till one runs out of die area for placing more repeaters or till the addition of repeaters does not improve wire delay.
Eq. (3) represents the case when repeaters are inserted with the Energy-Delay Product minimization strategy discussed in the repeater models section. Width of wires is equal to spacing between wires.

The wiring efficiency factor for intermediate and semi-global levels has two sources. The first source is via blockage due to vias to higher levels of metal and due to repeaters. These are modeled based on [27]. The second source is power via blockage that is modeled based on [26]. Wire resistivity increases due to size effects are modeled as shown in [26].
Power computation and iteration: Once repeaters are assigned, the total chip power is calculated. Logic gate power is found using device widths calculated in Step 2 and formulate given in [18]. Local clock power is computed by extending models in [23]. Wire power is calculated based on the stochastic wiring distribution [8], and repeater power is calculated based on Step 8 and repeater power models given in [24]. Leakage power variability is modeled as discussed in [25]. If the total power calculated is different from the power estimate used for designing power distribution wiring, IntSim sets $Estimated\ power=\frac{Old\ estimated\ power+Calculated\ power }{2}$ and goes back to Step 5. For the next iteration, the number of repeaters is set as the value calculated in Step 8, Assignment of wires with repeaters. 因为有repeater的线在本地互连阶段是不知道的，有via，blockage，等等，在global阶段才确定repeater，所以，循环是为了确定repeater的数量是合理的。
Data output: When the simulation converges, the total number of wire levels, pitches of each wire level and a power estimate are output.

[8] R. Venkatesan, J. Davis, et al., “Optimal n tier multilevel interconnect architectures for GSI”, Trans. VLSI Systems, Dec 2001

[18] Models in BACPAC: www.eecs.umich.edu/~dennis/bacpac

[23]G. Chandra, P. Kapur, K. Saraswat, “Scaling trends for the on chip power dissipation”, Proc. Intl. Interconnect Technology Conference, 2002

[24] K. Banerjee, A. Mehrotra, “A power optimal repeater insertion methodology for global interconnects”, Trans. Electron Devices, Nov. 2002.

[25] S. Narendra, V. De, S. Borkar, D. Antoniadis, A. Chandrakasan, “Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18um CMOS,” J. of Solid State Circuits, Mar. 2004.

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IntSim: A CAD tool for Optimization of Multilevel Interconnect Networks