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APR

CTS Spec UnsyncPin RootPin based on Constraint and Netlist

April 14, 2019

Turbodebug check Design netlist about clock timing path: Fig. 1 Design/inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux #Constraint create_clock -name clk_ddl_test_fdbk [get_pin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/$NEG_OUTPUT ] -period $PHY_DDL_SCALED_CLK_PERIOD -waveform “0 $PHY_DDL_SCALED_HALF” #CTS Spec file #Excluded Output pin due to create_clock inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN GlobalUnsyncPin +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand0/hic_dnt_nand2/A1 +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand1/hic_dnt_nand2/A1 #—————————————————- # Clock Name : clk_ddl_test_fdbk #—————————————————- AutoCTSRootPin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN  

design flow simple

July 10, 2015

Simplify a general design flow post-floorplan should be: 1st timing driven placement according to constraints, skew/latency was considered as ‘ideal’ zero, optDesign –preCTS. 2nd CTS, optDesign –postCTS. Clock tree have insertion or propagation delay after CTS. 3rd routing, optDesign –postRoute, optDesign –hold -postRoute. Usually, fix setup violation first, then hold violation in order to obtain… read more »

set_disable_timing

April 14, 2019

Sometimes, it is necessary to add constraint, such as set_disable_timing to let tool ignore timing path which should not be checked, critical path would be fixed by tool correctly. set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_master/delay_0] set_disable_timing -from in1 -to pass [get_cells dll/dll_delay_line_clk_wr/delay_0] #ezp set_disable_timing -from in1 -to pass [get_cells dll_delay_line/delay_0] #ezp set_disable_timing -from in1… read more »

meet skew via constraint

July 6, 2015

setOptMode -ignorePathGroupsForHold {in2reg reg2reg in2out} -holdTargetSlack 0 -setupTargetSlack 0 -fixHoldAllowSetupTnsDegrade false setOptMode -holdFixingCells {BUFFER_NAME} setDelayCalMode -engine xxx -SIAware true -signoff true set_analysis_view -setup funcPostC_PVT_setup  -hold funcPostC_PVT_setup update_constraint_mode -name funcPostC -sdc_files “constraint_file_path” optDesign -postRoute -outDir ./rpts/fix_skew_setup update_constraint_mode -name funcPostC -sdc_files “constraint_file_path” setOptMode -fixHoldAllowSetupTnsDegrade true optDesign -postRoute -hold -outDir ./rpts/fix_skew_hold constraint file set DQS_TSEL_SEL {tsel_dqs_1_opad tsel_dqs_2_opad tsel_dqs_3_opad}… read more »

update clock latency

April 14, 2019

Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »

Prepare files and check netlist

January 23, 2019

1. Which library files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib 2. Which files are about design? Netlist, constraint, IO file, scan def 3. What should be checked before APR? Check library files,… read more »

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