Physical

Cadence Virtuoso

I used Cadence® Virtuoso® to design layout for Electromigration (EM) Test Pad for tape-out with Harris Corporation and ICAMR in Fall 2016, partner was Novati Technologies, Inc. who I submitted GDSII to. Map file was from MOSIS: https://www.eda.ncsu.edu/wiki/MOSIS_Layers. The test pad size: 120um x 120 um. Pitch: 250um, which means 130um spacing between 2 test… read more »

Modeling Power Terminology

The power a circuit dissipates falls into two broad categories: Static power Dynamic power Static Power Static power is the power dissipated by a gate when it is not switching – that is, when it is inactive or static. Static power is dissipated in several ways. The largest percentage of static power results from source-to-drain… read more »

Path delay in cross clock domain

Sometimes, for cross clock domain timing analysis, incorrect timing report from mistake Path Delay due to big source clock paths latency/skew or target paths latency/skew would lead tool report and fix timing violation wrongly. Designer analysis launch clock paths latency/skew and capture clock paths latency/skew, find out which path(s) is/are too long, for example, it… read more »

Band Theory

Problems 1. How does the band gap indicate whether or not your substance is an insulator, semiconductor or conductor? 2. What is the purpose of a p-type semiconductor? An n-type? 3. What is the purpose of understanding band theory? Answers 1. A very large band gap is indicative of an insulator–since it takes a great… read more »

PN junction

Figure A. A p–n junction in thermal equilibrium with zero-bias voltage applied. Electron and hole concentration are reported with blue and red lines, respectively. Gray regions are charge-neutral. Light-red zone is positively charged. Light-blue zone is negatively charged. The electric field is shown on the bottom, the electrostatic force on electrons and holes and the… read more »

FinFET and MOSFET

Understanding the FinFET semiconductor process -from Youtube How MOSFETs and Field-Effect Transistors work! -from Youtube

Prepare files and check netlist

Which files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib Which files are about design? Netlist, constraint, IO file, scan def  

Prepare files and check netlist

Which files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib Which files are about design? Netlist, constraint, IO file, scan def    

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