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Clock

same source create_generated_clock -add

April 14, 2019

#Constraint set CLK_PHASE_0_SRC “dummy_clk4x” set EDGES {1 3 5} set CLK_PHY_PORT “clk4x” set PERIOD [expr 0.833 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] set PHY_CLK_PERIOD $PERIOD set PHY_HALF [expr 0.5 * $PHY_CLK_PERIOD] set PHY_QUARTER [expr 0.25 * $PHY_CLK_PERIOD] set CTLR_CLK_PERIOD [expr 2 * $PHY_CLK_PERIOD] set PHY_DDL_CLK_PERIOD [expr 0.2 * $TOOL_TIME_SCALE * $LIB_TIME_SCALE] create_clock [get_ports $CLK_PHY_PORT ] -name dummy_clk4x… read more »

Clock Tree Latency Skew Uncertainty

April 14, 2019

Clock to a SoC/chip is like blood to a dog body. If you want the pet smart and strong, hematological system would be healthy. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the chip…. read more »

CTS Spec UnsyncPin RootPin based on Constraint and Netlist

April 14, 2019

Turbodebug check Design netlist about clock timing path: Fig. 1 Design/inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux #Constraint create_clock -name clk_ddl_test_fdbk [get_pin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/$NEG_OUTPUT ] -period $PHY_DDL_SCALED_CLK_PERIOD -waveform “0 $PHY_DDL_SCALED_HALF” #CTS Spec file #Excluded Output pin due to create_clock inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN GlobalUnsyncPin +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand0/hic_dnt_nand2/A1 +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand1/hic_dnt_nand2/A1 #—————————————————- # Clock Name : clk_ddl_test_fdbk #—————————————————- AutoCTSRootPin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN  

Clock divider and CTS

April 14, 2019

Turbodebug check Design netlist about clk div timing path: Fig. 1 Design/inst_clk_div Fig. 2, 3 Design/inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN Fig. 4 Design/inst_clk_div/inst_clk_div_dff/hic_dnt_out_reg/Q (constraint below create_generated_clock set it as RootPin, but design inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN as RootPin in CTS Spec file, as Fig. 4 Q pin (out_p) connects to Fig. 2 in0 actually) #Constraint create_clock [get_ports clk4x ] -name dummy_clk4x -period 0.5*0.833 -waveform… read more »

design flow simple

July 10, 2015

Simplify a general design flow post-floorplan should be: 1st timing driven placement according to constraints, skew/latency was considered as ‘ideal’ zero, optDesign –preCTS. 2nd CTS, optDesign –postCTS. Clock tree have insertion or propagation delay after CTS. 3rd routing, optDesign –postRoute, optDesign –hold -postRoute. Usually, fix setup violation first, then hold violation in order to obtain… read more »

Clock Tree Synthesis

April 14, 2019

In clock tree synthesis, do ONE thing only, insert CLK INV (NOT CKBUFF !) which could fix rising and falling transition/duty, to min clock tree latency and skew, balance sink/leaf pins which should be balanced, don’t balance pins which should not be balanced. CTS Macro Model Let tool know the segment of clock path latency which… read more »

OCV

July 6, 2015

For chip tapeout, physical design must clean timing/skew/transition violations based on OCV (on chip variation) derating in signoff STA environment. http://www.techdesignforums.com/practice/guides/on-chip-variation-ocv/ For example, when check setup violation, launch path is late, clock cell delay times 1.039, data cell delay times 1.077, capture path is early, clock cell delay times 0.961, clock net delay times 0.915…. read more »

update clock latency

April 14, 2019

Pre CTS or placement, clock latency, skew, transition are considered as ideal zero, but tool add clock buffer/inverter in CTS period in order to minimums clock latency/skew/transition as much as possible, clock tree has insertion delay after CTS. Post CTS and post route, comparing to datapath delay change, clock path in launch path ‘stretch’, especially… read more »

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