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Netlist

Symbolic Netlist to Innovus-friendly Netlist

November 11, 2019

  run_lc_dc.csh \rm lc_shell*.log \rm dc_shell*.log ############################### # 1 gen *.db by *.lib # for example, AND_OR_INV.db. ############################### # get asap7nm/AND_OR_INV.db lc_shell -64bit -f gen_AND_OR_INV_db.tcl > lc_shell_AND_OR_INV_db.log ############################### # 2 syn symbolic netlist to Innovus-friendly *.v by *.db ############################### # test simple circuit (MAJ1-INV-MAJ2 symbolic expression) netlist by AND_OR_INV.db dc_shell -64bit -f MAJ1-INV-MAJ2_syn_AND_OR_INV_db.tcl > dc_shell_MAJ1-INV-MAJ2_syn_AND_OR_INV_db.log… read more »

CTS Spec UnsyncPin RootPin based on Constraint and Netlist

August 3, 2015

Turbodebug check Design netlist about clock timing path: Fig. 1 Design/inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux #Constraint create_clock -name clk_ddl_test_fdbk [get_pin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/$NEG_OUTPUT ] -period $PHY_DDL_SCALED_CLK_PERIOD -waveform “0 $PHY_DDL_SCALED_HALF” #CTS Spec file #Excluded Output pin due to create_clock inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN GlobalUnsyncPin +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand0/hic_dnt_nand2/A1 +inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand1/hic_dnt_nand2/A1 #—————————————————- # Clock Name : clk_ddl_test_fdbk #—————————————————- AutoCTSRootPin inst_adrctl_slice_bist_ddl/inst_ddl_fdbk_clk_mux/inst_mux_nand2/hic_dnt_nand2/ZN

Clock divider and CTS

July 30, 2015

Turbodebug check Design netlist about clk div timing path: Fig. 1 Design/inst_clk_div Fig. 2, 3 Design/inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN Fig. 4 Design/inst_clk_div/inst_clk_div_dff/hic_dnt_out_reg/Q (constraint below create_generated_clock set it as RootPin, but design inst_clk_div/inst_clk_div_mux/inst_mux_nand2/hic_dnt_nand2/ZN as RootPin in CTS Spec file, as Fig. 4 Q pin (out_p) connects to Fig. 2 in0 actually) #Constraint create_clock [get_ports clk4x ] -name dummy_clk4x -period 0.5*0.833 -waveform… read more »

Prepare files and check netlist

June 21, 2015

Which files do backend engineers need? Timing: lib RC delay: capTable, QRC tech, QRC lib Physical: lef, gds Route rule: tech lef, tech file Xtalk: cdb Power: VoltageStorm tech, VoltageStorm lib Which files are about design? Netlist, constraint, IO file, scan def    

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